SENIOR/LEAD ASIC ENGINEER

Lead ASIC DFT EngineerLocation: Remote (Must align with PST) Pay Rate: 80–90/hr (W2) Visa: USC, GC, EAD (No OPT/CPT)🔹 OverviewSenior-level ASIC DFT expert responsible for end-to-end DFT architecture, implementation, verification, and silicon debug for complex ASIC/SoC designs.🔹 Key Skills (Must Have)Scan, ATPG, MBIST, LBISTTiming Simulation, SDF, SDCPattern Retargeting / PortingDiagnosis, DRCsTools: TetraMax, DFTMax🔹 Experience10+ years in ASIC DFT (hands-on)🔹 ResponsibilitiesLead DFT architecture, implementation & sign-offDrive scan insertion, scan chains & compression flowsOwn MBIST/LBIST integration and debugPerform silicon debug, failure analysis & root causeDevelop DFT constraints (SDC) & timing analysisSupport ATPG generation, simulation & coverage closureWork on JTAG, boundary scan, iJTAGCollaborate across RTL, PD, STA, validation teamsMentor junior engineersDevelop automation scripts (TCL/Perl/Python)🔹 RequirementsStrong DFT fundamentals & fault models knowledgeExpertise in scan, ATPG, MBIST, JTAG, debugExperience with Synopsys / Cadence / Siemens toolsPost-silicon validation experienceLarge SoC & hierarchical DFT exposure🔹 PreferredTessent / SSN toolsYield analysis & manufacturing test optimizationMulti-node ASIC experience #HireFinder#LI-PROMOTED#LI-Remote